Systems are normally implemented by mounting a number of discrete components on a printed circuit board. However, implementing the circuitry of discrete components in a single integrated circuit chip yields advantages of cost reduction, low power consumption, space savings and ruggedness. Such a single chip (also called "system-on-chip" and abbreviated as "SOC") 1 (see FIG. 1A) has a number of functional modules 2-9 that provide functions different from each other, and may include, for example, a central processing unit (CPU) module 2, a random access memory (RAM) module 3, and a liquid crystal display (LCD) module 4. See page 85 of Electronic Engineering Times, Mar. 29, 1999(an advertisement). It is well known to permanently couple (i.e. hardwire) functional modules 2-9 to a group of predetermined pads 1A-1P (not all pads in FIG. 1 are labeled) for coupling to external circuitry.
Among the pads (e.g. pads 1I-1N) that are hardwired to CPU module 2, some pads (e.g. pads 1I-1K) may be used in a multiplexed manner by CPU module 2. Specifically, Intel 8086 and Zilog Z8000 CPUs provide a 16-bit address/data bus that multiplexes the low-order sixteen address bits with the 16-bit data word. Additionally, the 8086 CPU multiplexes four address bits with four status signals on four separate pads. Also, the Intel 8085 CPU has an 8-bit address/data bus that multiplexes the lower half of a 16-bit address with the 8-bit data byte. See pages 172-173 and 209-212 of the book entitled "Microprocessor System Design Concepts" by Nikitas A. Alexandridis, Computer Science Press, 1984.
Moreover, Purcell et al. (see U.S. Pat. No. 5,379,356) describe a single chip (called "CL950 chip" at column 6, lines 5-9) having at least a processor, a decoder coprocessor, and a motion compensation coprocessor that are connected to a global bus (see column 6, lines 10-13 and lines 17-33). The global bus in turn is coupled via "Pad and FFS" to a memory bus that is external to the single chip (e.g. coupled to DRAM as described at column 6, lines 53-55). Purcell et al. also state that "by looping back the CAS signal on the output pin, this embodiment can monitor the time at which the CAS signal is asserted at the external DRAM. Therefore, the uncertainty as to whether the external DRAM receives the column address is removed . . . " (column 7, lines 3-8). See also U.S. Pat. No. 5,598,514 for another description of the global bus.
U.S. Pat. No. 5,701,507 describes an integrated circuit having several groups of processors and memories, wherein "each processor . . . has direct communication with each memory . . . via a crossbar link . . . " (column 3, lines 1-11). Moreover, U.S. Pat. No. 5,742,180 (see FIG. 1B) describes a gate array, wherein "nine (3.times.3) subarrays are connected by associated bidirectional cross bars . . . [c]communication at the edge of the nine subarrays goes off-chip via input/output pads or pins . . . " (column 6, lines 28-31).
Furthermore, U.S. Pat. No. 5,036,473 describes a "partial crossbar interconnect [in which] the I/O pins of each logic chip are subdivided into proper subsets, using the same division on each logic chip. The pins of each crossbar chip are connected to the same subsets of pins from each and every logic chip. Thus crossbar chip `n` is connected to subset `n` of each logic chip's pins. As many crossbar chips are used as there are subsets, and each crossbar chip has as many pins as the number of pins in the subset times the number of logic chips. Each logic chip/crossbar chip pair is interconnected by as many wires, called paths, as there are pins in each subset". See column 15, line 63 to column 16, line 6.